While various improvements in design approaches and manufacturing methods have led to increases in the speed at which data is processed within an integrated circuit, an important part of an integrated circuit's function continues to be how internal data signals are translated into output data signals for use by other devices. The propagation of data signals within an integrated circuit occurs on conductive lines of relatively small dimensions. Thus, the electrical loads presented by the internal conductive lines can be driven with relatively small transistors that draw small amounts of current. This is in contrast to the propagation of signals external to the integrated circuit device. In order to transmit data signals externally, an integrated circuit must drive a much larger capacitive and inductive load. The external load typically includes a bond wire that carries the electrical signal from the integrated circuit to a conductive lead frame. The lead frame provides the conductive leads (or pins) of the integrated circuit package. When the integrated circuit is use, the package pin will be electrically connected to other lines in an electronic system (e.g., soldered to a conductive line on a printed circuit board).
In order to ensure that the relatively large external loads are driven rapidly between various voltage levels, an integrated circuit typically includes an output buffer circuit for each output signal. Output buffer circuits include large semiconductor circuit elements that are capable of providing ("sourcing" or "sinking") the relatively large amounts of current required to rapidly charge and discharge the external loads, and thereby generate an output signal.
An example of a prior art output buffer circuit is set forth in a schematic diagram in FIG. 1. The output buffer circuit is designated by the general reference character 100, and is shown to include an input latch 102, a first pre-drive circuit 104, a second pre-drive circuit 106 and an output driver circuit 108. The input latch 102 includes two cross-coupled inverters I100 and I102. The input latch 102 receives an input data signal (DATA), and latches the value to provide an inverse data signal (DATA_) to the first and second pre-drive circuits (104 and 106).
The first pre-drive circuit 104 receives the DATA.sub.-- signal and an output enable signal (OE_), and in response to these signals, drives a first pre-drive node 110 between a high pre-drive potential and a low pre-drive potential. When the OE_ signal is high, the first pre-drive circuit 104 is disabled, and the first pre-drive node 110 is driven to a disable (high) potential. When the OE_ signal is low, the first pre-drive circuit 104 is enabled, and the first pre-drive node 110 voltage will follow from the DATA signal value. When the DATA_ signal is high, first pre-drive node 110 will be driven high. When the DATA_ signal is low, the first pre-drive node 110 will be driven low. The first pre-drive circuit 104 includes a two-input NOR gate G100 that receives the OE.sub.-- signal and the DATA_ signal as inputs. The output of gate G100 is provided as an input to an inverter I104. The output of inverter I104 drives the first pre-drive node 110.
The second pre-drive circuit 106 receives the DATA_ signal and a second output enable signal OE. The signal OE is the inverse of the OE_ signal. In response to the DATA.sub.-- and OE signal, the second pre-drive circuit 106 drives a second pre-drive node 112 between a enabling (high) pre-drive potential and a disabling (low) pre-drive potential. In a similar fashion to the first pre-drive circuit 104, when the OE signal is low, the second pre-drive circuit 106 is disabled, and the second pre-drive node 112 is driven low. When the OE signal is high, the second pre-drive circuit 106 is enabled, and the second pre-drive node 112 voltage will follow the DATA_ signal value. The second pre-drive circuit 106 includes a two-input NAND gate G102 that receives the OE signal and the DATA_ signal as inputs. The output of gate G102 is provided as an input to an inverter I106. The output of inverter I106 drives the second pre-drive node 112.
The output driver circuit 108 drives an output node 114 to either a high supply voltage (VDD) or a low supply voltage (VSS) depending upon the potential at the first pre-drive node 110 and second pre-drive node 112. The output driver circuit 108 includes p-channel metal-oxide-semiconductor (MOS) transistor P100 having a source-drain path connected between the VDD voltage and the output node 114. The gate of transistor P100 is coupled to the first pre-drive node 110. In a similar fashion, an n-channel MOS transistor N100 has a source-drain path connected between the output node 114 and the VSS voltage. The gate of transistor N100 is driven by the second pre-drive node 112. The output node 114 provides a data output signal DATA_OUT.
The operation of the prior art output buffer circuit 100 is best understood with reference to FIG. 2 in conjunction with FIG. 1. FIG. 2 is a timing diagram illustrating the OE signal, the DATA signal, and the DATA_OUT signal. In addition, the response of the first pre-drive node 110 and the second pre-drive node 112 are also set forth as waveforms "110" and "112" respectively.
Referring now to FIG. 2 in conjunction with FIG. 1, at time t0 the OE signal is low (and the OE.sub.-- signal is high), disabling the output driver circuit 100. The first pre-drive circuit 104 drives the first pre-drive node 110 high, turning off transistor P100. In the same fashion, the second pre-drive circuit 106 drives the second pre-drive node 112 low, turning off transistor N100.
At time t1, the OE signal transitions high (forcing OE_ low), and thereby enabling the output buffer circuit 100. The high DATA signal propagates through the input latch 102 driving the DATA_ signal low. With the OE_ and DATA_ signals low, the output of gate G100 is driven high. Inverter I104 drives the first pre-drive node 110 low, turning on transistor P100. In this manner, the DATA_OUT signal is driven high to the VDD voltage. At the same time, the low DATA.sub.-- signal and high OE signal are received by the second pre-drive circuit 106. The output of gate G102 remains high, and inverter I106 maintains the second pre-drive node 112 low, keeping transistor N100 off.
At time t2, with the OE signal still high, the DATA signal makes a first transition from high to low. The input latch 102 drives the DATA_ signal high. The high DATA_ signal results in the output of gate G100 going low, and inverter I104 drives the first pre-drive node 110 high. Transistor P100 is turned off, isolating the output node 114 from the VDD voltage. At the same time, with the OE and DATA.sub.-- signals high, the output of gate G102 is driven low, and inverter I106 drive the second pre-drive node 112 high, turning on transistor N100. The output node 114 is thus coupled to the VSS voltage, driving the DATA_OUT signal low.
At time t3, the DATA signal makes a second transition from low to high. The input latch 102 drives the DATA_ signal low. With a low DATA_ signal and a low OE_ signal, the output of gate G100 is driven high once more, and inverter I104 drives the first pre-drive node 110 low. Transistor P100 is turned on, and the DATA_OUT signal is driven high once again. At the same time, as the DATA_ signal goes low at the input of gate G102, the output of gate G102 is driven high, resulting in transistor N100 being turned off.
At time t4, the OE signal returns low, placing the output buffer circuit 100 in the disabled state once again. As described for time t0, the first pre-drive node 110 is driven high, turning off transistor P100, and the second pre-drive node 112 is driven low, turning off transistor N100.
In the prior art example of FIG. 1, transistors P100 and N100 are very large devices that are capable of rapidly drawing or discharging current to thereby drive the output node 114 between logic values. A drawback to the prior art circuit of FIG. 1 can arise out of the inherent inductance presented by the output load coupled to the output node 114. As transistors P100 and N100 switch on and off, the rate at which current is drawn through the load (the "di/dt") can be considerable. The di/dt in conjunction with inherent load inductance and supply line inductance can generate undesirable voltage changes at the output node 114 (often referred to as "ground bounce" or "supply bounce"). The supply line inductance typically arises from the portions of the lead frame that supply the power supply voltages (VCC and VSS) to the integrated circuit.
A second prior art example, set forth in FIG. 3, illustrates an output buffer circuit that can reduce ground bounce by dividing the output driving action into a first driving action followed by a second, subsequent driving action. The second prior art output buffer circuit is designated by the general reference character 300, and is shown to include an input latch 302, a first pre-drive circuit 304, a second pre-drive circuit 306, and an output driver circuit 308. Like the circuit of FIG. 1, the input latch 302 includes two cross-coupled inverters I300 and I302 that receive and latch an input data signal (DATA), to provide an inverse data signal (DATA_) for use by the first and second pre-drive circuits (304 and 306).
Unlike the first and second pre-drive circuits (104 and 106) of FIG. 1, which each drive a single pre-drive node, the first and second pre-drive circuits (304 and 306) of FIG. 3, each drive two pre-drive nodes. As shown in FIG. 3, the first pre-drive circuit 304 drives a first pre-drive node 310 and a second pre-drive node 312. Likewise, the second pre-drive circuit 306 drives a third pre-drive node 314 and a fourth pre-drive node 316. In operation, each pre-drive circuit (304 and 306) will drive one of its pre-drive nodes first, and then following a delay, will drive the other pre-drive node. In particular, when the DATA signal goes high, the first pre-drive circuit 304 will drive the first pre-drive node 310 low, and then following a delay, drive the second pre-drive node 312 low. When the DATA signal goes low, the second pre-drive circuit 306 will first drive the third pre-drive node 314 high, and then following a delay, drive the fourth pre-drive node 316 high.
The first pre-drive circuit 304 is shown to include a two-input NOR gate G300 that receives an output enable signal OE_ and the DATA_ signal. The output of gate G300 is connected to the first pre-drive node 310 by way of an inverter I304 and a resistor R300. In addition, the output of gate G300 is connected to the second pre-drive node 312 by a first inverting delay circuit D300. The inverting delay circuit D300 inverts and delays the output of gate G300. The second pre-drive circuit 306 includes a two-input NAND gate G302 that receives an output enable signal OE and the DATA_ signal. The output of gate G302 is connected to the third pre-drive node 314 by an inverter I306 and a resistor R302. The output of gate G302 is also connected to the fourth pre-drive node 316 by a second inverting delay circuit D302.
The output driver circuit 308 drives an output node 318 between a high supply voltage VDD and low supply voltage VSS to generate a data output signal DATA_OUT. Unlike the circuit of FIG. 1, which drives its output node 114 high by a single charge path (the source-drain path of transistor P100), the output driver circuit 300 of FIG. 3 drives the output node 318 high with two charge paths. A first path is created by a first p-channel MOS drive transistor P300 which is controlled by the potential at the first pre-drive node 310. A second path is created by a second p-channel MOS drive transistor P302 which is controlled by the potential at the second pre-drive node 312. The output driver circuit 308 includes two discharge paths as well. A first discharge path is provided by an n-channel third drive transistor N300 which is controlled by the potential at the third pre-drive node 314. A second discharge path is created by an n-channel fourth drive transistor N302 which is controlled by the potential at the fourth pre-drive node 316.
The operation of the output buffer circuit 300 is described by a timing diagram in FIG. 4. FIG. 4 illustrates an OE signal, a DATA signal, and a DATA_OUT signal. In addition, the resulting responses of the first through fourth pre-drive nodes (310, 312, 314 and 316) are shown as waveforms "310," "312," "314" and "316," respectively.
Referring now to FIG. 4 in conjunction with FIG. 3, at time t0, the OE signal is low, resulting in the output buffer circuit 300 being disabled. The resulting high OE_ signal at the input of gate G300, forces the first and second pre-drive nodes (310 and 312) high, turning off transistors P300 and P302. Within the second pre-drive circuit 306, the low OE signal forces the output of gate G302 high. As a result, the third and fourth pre-drive nodes (314 and 316) are forced low, turning off transistors N300 and N302.
At time t1, the OE signal transitions high, enabling the output buffer circuit 300. With the OE_ signal now low and the DATA_ signal low, the output of gate G300 goes high. As a result, the first pre-drive node 310 will be driven low, turning on transistor P300. In this manner, current will begin flowing through transistor P300. The resistor R300 and size of transistor P300 helps reduce the rate at which the first pre-drive node 310 is charged, thereby reducing the magnitude of the di/dt generated when transistor P300 turns on.
Following the delay established by inverting delay circuit D300, the second pre-drive node 312 will be driven low, turning on transistor P302. Transistor P302 will then complete the charging of the output node 318. While transistors P300 and P302 turn on sequentially, the third and fourth pre-drive nodes (314 and 316) remain low, keeping transistors N300 and N302 turned off.
At time t2, the DATA signal makes a first transition from a high logic value to a low logic value. The input latch 302 latches the new DATA signal value, driving the DATA_ signal high. The high DATA.sub.-- signal is applied to the first pre-drive circuit 304, driving the output of gate G300 low. The first pre-drive node 310 is driven high, turning off transistor P300. Likewise, the second pre-drive node 312 is subsequently driven high by delay circuit D300, causing transistor P302 to turn off.
At the same time, the high DATA_ signal, in combination with the high OE signal, results in the output of gate G302 being driven low. The third pre-drive node 314 is driven high, turning on transistor N300 to begin driving the output node 318 low. Resistor R302 and the size of transistor N300 limit the rate at which the third pre-drive node is discharged, thereby reducing the di/dt caused by transistor N300. Following a delay established by inverting delay circuit D302, transistor N302 turns on, completing the discharge of the output node 318. In this manner, the DATA_OUT signal is driven low in response to a low DATA signal input.
At time t3, the DATA signal makes a second transition from low to high. The input latch 302 latches the new data value forcing the DATA_ signal low. With the DATA_ signal low and the OE_ signal low, the first pre-drive node 310 is driven low once again, turning on transistor P300. The output node 318 will begin charging, but at a reduced di/dt rate. After the delay established by delay circuit D300, the second pre-drive node 312 is driven low and transistor P302 will turn on, further charging the output node 318. At the same time, the second pre-drive circuit 306 will drive the third pre-drive node 314 and fourth pre-drive node 316 low, turning off transistors N300 and N302. In this manner, the DATA_OUT signal is driven high in response to a high DATA signal input.
At time t4, the OE signal falls, disabling the output driver circuit 300. The high OE_ signal and low OE signal result in the outputs of gates G300 and G302 being low and high, respectively, regardless of the DATA_ value. As a result, transistors P300, P302, N300 and N302 are all turned off, allowing the output node 318 to float in a high impedance state.
While the prior art output buffer circuit of FIG. 3 can reduce di/dt values required to rapidly drive the output node 318, the output buffer circuit can require considerable area, as four large driver transistors (P300, P302, N300 and N302) are required.
Other output driver circuits, having only two driver devices, have managed to reduce di/dt values, by carefully biasing the pre-drive nodes that control the driver devices. Such an approach requires complex biasing circuits, and so can be difficult to implement. In addition, such biasing circuits may also require substantial increases in the amount of area required.
A further factor can contribute to the difficulties of implementing output buffer circuits. This factor is the desire to have integrated circuits operate at more than one power supply voltage. For example, many integrated circuit devices may be designed to operate at a first "high" power supply voltage of five volts as well as a "low" power supply voltage, such as 3.3 volts. An output buffer circuit that may operate at one power supply voltage with sufficient speed and low di/dt response, may not be appropriate for another power supply voltage. In particular, the output buffer circuit 100 of FIG. 1 may function adequately at a low power supply voltage. The low VDD value will result in lower di/dt magnitudes when the drive transistors (N100 and P100) switch on and off. However, were the power supply raised to a higher level, the resulting higher VDD value could cause the di/dt values to increase thereby introducing supply bounce. Similarly, the output buffer circuit 300 of FIG. 3 may function well at a high power supply voltage by reducing the resulting di/dt as previously described. However, at a low power supply voltage the output buffer circuit 300 may be too slow, taking too long to drive the output node 318 between the smaller VDD voltage and VSS voltage.
It would be desirable to have an output buffer circuit that provides a high operating speed and low di/dt response for both a high and a low supply voltage level. At the same time, it would desirable to do so without requiring overly complex timing circuits or additional area for the implementation of a large number of output drive devices.